1. Technology Field
The present invention is directed to a memory management method and more particularly, to a memory management method and a memory control circuit unit and a memory storage apparatus using the method, which can accurately detect a page being programmed when an abnormal power failure occurs.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 players in recently years, the consumers' demand to storage media has increased drastically. Because a rewritable non-volatile memory is capable of providing features such as data non-volatility, low power consumption, small volume, and non-mechanical structure, high reading and writing speed, the rewritable non-volatile memory has become the most adaptable memory applied in a portable electronic product, e.g., a notebook computer. A solid state drive (SSD) is a storage apparatus which utilizes a flash memory as its storage medium. Therefore, the flash memory industry has become a very popular part of the electronic industry in recent years.
FIG. 1 is a schematic diagram illustrating a flash memory device according to the related art.
Referring to FIG. 1, a flash memory device 1 includes a charge-trapping layer 2 for storing electrons, a control gate 3 for applying a voltage, a tunnel oxide layer 4, and an interpoly dielectric layer 5. When data is to be written into the flash memory device 1, a threshold voltage of the flash memory device 1 may be changed by injecting electrons into the charge-trapping layer 2. Accordingly, a digital-level state of the flash memory device 1 is defined to implement a function of storing data. Here, the process of injecting the electrons to the charge-trapping layer 2 is referred to as a programming process. By contrast, when the stored data is to be removed, the injected electrons are removed from the charge-trapping layer 2, and thereby the flash memory device 1 is restored back to the default state before programming.
During the operation of a memory storage apparatus, if an abnomial power failure occurs, data being written when the abnormal power failure occurs may have errors and should be considered as invalid data. In a conventional determination method, all pages in the memory storage apparatus are scanned when the memory storage apparatus is powered on, and if the number of error bits in a page is over a threshold, the memory storage apparatus determines the data stored in the page as invalid data. However, an issue that valid data having a great number of error bits caused by other reasons (e.g., data retention, reading interference and durability for erasing and writing) is determined as the invalid data may occur in this method, which may lead to serious errors during the operation of the memory storage apparatus. Therefore, how to accurately determine the page being written when the abnormal power failure has become one of the major subjects for technicians of the art.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.